The present invention relates to a method and apparatus for providing a program counter value within a central processing unit of a microprocessor or microcontroller. The program counter contains the address in a memory of an instruction to be executed by a central processing unit. Within modern microprocessors, such as a superscalar microprocessor, exists the possibility of executing multiple instructions in parallel. Furthermore, the size of each instruction may vary. The program counter which indicates the memory location of a currently executed instruction has to be updated after execution of one or more instructions executed in parallel. Thus, the next program counter value depends on the current program counter value and the number of bytes constituting the issued instructions. For example, the number of bytes issued can vary from two to eight within a microprocessor who is capable of issuing a minimum of one 16-bit instruction (2 bytes) and a maximum of two 32-bit instructions (8 bytes), as each instruction can be two or four bytes long and up to two instructions could be issued in any one cycle.
In a pipelined microprocessor, the number of actual instructions which can be issued and the size of these instructions will be known at a relatively late time. Thus, very little time is left to calculate the next program counter value. The value is required to be calculated without serializing the addition based on the number of bytes issued to save as much time as possible.